In modem integrated-circuit design, embedded memories occupy a large area of a chip. In microprocessors, for example, embedded memories can occupy more than 30% of the chip area, and in a system-on-a-chip (SoC), they can exceed 60%. The memory array is typically the densest physical structure on the chip and is usually made from the smallest geometry process features available.
To test an embedded memory, a variety of methods have been developed. One known method utilizes unmodified scan cells to load test vectors from an external tester and to capture the output responses from the memory. This method, however, can involve long test times because a large number of shifts are necessary to load the appropriate test values (each shift consumes one clock cycle). Thus, this method is most useful for smaller memories where the number of shifts can be minimized and where there is no area overhead available for memory built-in self-test (MBIST) hardware. Another approach uses MBIST hardware to generate and analyze test results directly on the chip. The known MBIST method involves building onto the chip a test-vector generator, an output-response analyzer, and an algorithmic sequencer. Some of the advantages of using an MBIST architecture are that only a few interface signals are needed to control the MBIST hardware and the testing of the memory can be performed at-speed. A major drawback of conventional MBIST circuits, however, is that a plurality of multiplexers are placed before the inputs of the memory-under-test in order to input the test vectors. These multiplexers produce a delay in the system paths to the memory inputs, and thus-create a permanent penalty in memory performance. Additionally, when the memory is tested at-speed, delay faults in the memory and delay faults in the logic around the memory may escape from being detected. For example, suppose that there is a system path which starts at a register, propagates through five gates, and reaches a memory input. A test vector from a conventional MBIST circuit will not propagate through the five gates when the memory is being tested. Instead, the MBIST circuit will apply the test vectors directly to the memory inputs through the multiplexers. Consequently, certain delay faults cannot be detected by the conventional MBIST architecture. Similar problems are experienced along the output paths of the memories.